The present invention relates to an initializing/diagnosing system in an on-chip multiprocessor system, which is a multiprocessor system including a plurality of central processing elements (CPUs), and other elements which are diagnosed, such as a main memory element, a main memory access controller, and an input output processor (IOP) are mounted on a single Large Scale Integration (LSI).
A conventional on-chip multiprocessor system is shown in FIG. 6. An on-chip multiprocessor system 200 is connected to an initialization/diagnosis control processor 20. Initialization/diagnosis control processor 20 is a processor dedicated to initialization/diagnosis control implemented by another LSI. Initialization/diagnosis control processor 20 is independent of on-chip multiprocessor system 200. On-chip multiprocessor system 200 includes a CPU group 21 including CPUs 211 to 21m (m is an integer which satisfies m>0), a main memory access controller 22, a main memory element 23, and an IOP group 24 including IOPs 241 to 24n (n is an integer which satisfies n>0).
Initialization/diagnosis control processor 20 starts the operation of initializing/diagnosing CPU group 21, main memory access controller 22, main memory element 23, and IOP group 24 by receiving an electric confirmation signal, when power is applied to on-chip multiprocessor system 200, as a trigger signal from a system control section, which controls “system start-up” and “general corrective process” regarding on-chip multiprocessor system 200. In this embodiment, the electric confirmation signal is a CPU initialization/diagnosis start instruction signal outputted from the system control section, and is typically represented by a signal notifying the application of power to on-chip multiprocessor system 200.
The initializing/diagnosing operation by initialization/diagnosis control processor 20 is performed by writing and reading data using a diagnosing path such as a scan path which is provided on each of the elements to be diagnosed, including CPU group 21, main memory access controller 22, main memory element 23, and IOP group 24.
The initialization/diagnosis control processor 20 outputs the diagnosed results to the system control section. The system control section disconnects the faulty elements however, in some situations, some non-faulty elements may also be disconnected.
In the conventional system, an initialization/diagnosis control processor that is independent of the CPUs and non-CPU to-be-diagnosed elements must be provided. This creates a problem because the number of hardware elements required to drive the on-chip multiprocessor system is increased.
The initialization/diagnosis control processor is usually designed with an inexpensive technology to reduce the manufacturing cost of the on-chip multiprocessor system and thus, the clock frequency of the initialization/diagnosis control processor is lower than the clock frequency (clock frequency of the CPUs and the like) at normal operation of the on-chip multiprocessor system. This creates a problem because the initializing/diagnosing operation becomes slow.
When the clock frequency of elements which are diagnosed, such as the CPUs, is different from the clock frequency of the initialization/diagnosis control processor, another problem occurs because it is necessary to also synchronize control.
A conventional diagnosing system for a multiprocessor is disclosed in Japanese laid-open publication Hei No. 3-19069. The diagnosing system for a multiprocessor includes a plurality of element processors, each of which compares its own processed result with processed results of another element processors, and a majority circuit which receives the compared results from the processors and determines the presence of an abnormal element processor by using majority logic. The system has the majority circuit, however, it does not diagnose the entire on-chip multiprocessor system, including non-CPU elements.